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Fragster | 10. July 2022

All information about the world’s first RISC-V laptop

According to a report by Phoronix, the world’s first laptop running the RISC-V instruction set named ROMA is available for pre-order. The laptop manufactured by DeepComputing and Xcalibyte in China features a quad-core RISC-V processor, up to 16GB of LPDDR4/LPDDR4X memory and up to 256GB of storage, and supports RISC-V and most Linux operating systems. 

ROMA represents an important milestone in the RISC-V community. The architecture has not yet caught on in the consumer area; it is more common in the server industry. However, unlike traditional consumer laptops, this RISC-V model is aimed at developers who use the RISC-V instruction set to develop applications, so it can hardly be used as a traditional laptop.

100 laptops can be pre-ordered now

According to the DeepComputing press release, the laptop will use a “world-first” 12nm/28nm SoM package. The chip will contain four cores as well as a GPU and NPU for 3D/2D and AI acceleration. There will only be 100 ROMA notebooks available to pre-order now. Each ROMA will be equipped with a unique NFT, and you can even have your name or company name engraved on the notebook if you wish.

What is RISC-V?

RISC-V is a fairly old instruction set by today’s standards, but it has only recently been widely adopted by the computer industry. RISC-V has many advantages over mainstream instruction sets such as x86, ARM, and AMD64. The biggest of them is full open-source licensing, so anyone can use the architecture. It differs fundamentally from x86 and ARM, which require commercial licenses and fees for companies to acquire and use the technology.

DeepComputing RICS V laptop

From a performance standpoint, the key differentiator of RISC-V compared to x86 and AMD64 is its use of a simpler RISC architecture rather than CISC.

RISC, or Reduced Instruction Set Computer, is based on the idea of ​​using simple instructions that execute in a single clock cycle. The disadvantage of this technique is that it requires more code to complete a task, but the advantages are improved battery life and power efficiency. (In case you’re wondering, ARM chips also use RISC instead of CISC to improve battery life in mobile devices, but the implementation is quite different).

CISC and RISC

CISC, or Complex Instruction Set Computer, is the opposite of RISC. Rather than executing instructions in a single clock cycle, the goal is to complete tasks in as few lines of code as possible, which often means instructions take multiple clock cycles. While this results in higher power consumption, it is more beneficial for developers because CISC requires less code overall.

RISC-V can be used in the consumer space, but is limited to the enterprise market due to competition from other instruction sets. Almost all chips based on RISC-V are intended for AI or HPC or other high-level computing tasks, but RISC-V could catch on as more laptops and desktops with such chips come to market. While the ROMA may satisfy developers, it doesn’t stop users from using the notebook for other tasks.

Image credit: DeepComputing